1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and particularly to a method of forming a semiconductor device with a bipolar transistor having a lateral structure.
2. Description of the Related Art
One point of the superiority of a bipolar LSI to CMOS-LSI, resides in high-speed performance of a transistor per se and high-speed performance that originates from the magnitude or level of current drive capacity. It has however been said that since power consumption is relatively high, the bipolar LSI has not been suited to high-scale high integration.
In terms of the power consumption, attention has been given to a CMOS structure. Thus, there have been proposed several circuit systems or modes in which even in a bipolar device, PNP and NPN transistors are used for its basic circuit on the pattern of the CMOS structure to thereby maintain or increase its high-speed performance and high drive capacity, thus making it possible to significantly reduce power consumption.
There is known a lateral bipolar transistor provided on an SOI (Silicon On Insulated) substrate 1403, which has been described in, for example, Japanese Patent Application Laid-Open No. Hei 5(1993)-21446. A sidewall insulating layer 21 is formed on each side face of a polycrystal silicon layer 70 used as a base drawing or withdrawal electrode 7 as shown in FIG. 13. A P type impurity is ion-implanted in a base-emitter opening with the base drawing electrode 7 and the sidewall insulating layer 21 as masks, whereby a P type base region 6B having a thickness substantially equal to the sidewall insulating layer 21 is formed.
However, the conventional lateral bipolar transistor is accompanied by a problem that a minimum processing width based on photolithography is restricted, and if implantation is made over a given depth even in the case of a process using a self-alignment reduction process for sidewalls or the like, then an implanted impurity collides with a substance to be implanted and is hence reflected, thus allowing it to spread over an implantation width, whereby an intrinsic base width is expanded due to lateral channeling.
Therefore, the base width cannot be narrowed. As a result, the time required for carries in a base high in rate contributing to the transistor high-speed performance to run will increase.
An object of the present invention is to provide a semiconductor device manufacturing method of narrowly forming a base width, and a semiconductor device manufactured by the same method.